Hazard-free synthesis and decomposition of asynchronous circuits

Ren Der Chen, Jer Min Jou, Yeu Horng Shiau

研究成果: Conference contribution

摘要

In this paper, we solve the problems of hazard-free synthesis and decomposition of asynchronous speed-independent circuits for technology mapping. All high fanin gates are decomposed into gates that can be implemented by the gate library. We first analyze the conditions where hazards may occur during decomposition and then give corresponding strategies to solve them. All the proposed algorithms have been implemented and applied to the asynchronous benchmarks to verify their correctness. Experimental results show that less area is required in our final implementations.

原文English
主出版物標題Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999
發行者Institute of Electrical and Electronics Engineers Inc.
頁面185-188
頁數4
ISBN(電子)078035012X
DOIs
出版狀態Published - 1999
事件4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999 - Wanchai, Hong Kong
持續時間: 1999 1月 181999 1月 21

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
1999-January

Conference

Conference4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999
國家/地區Hong Kong
城市Wanchai
期間99-01-1899-01-21

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 電腦科學應用
  • 電腦繪圖與電腦輔助設計

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