Hierarchical test control architecture for core based design

Kuen Jong Lee, Cheng I. Huang

研究成果: Conference article

11 引文 斯高帕斯(Scopus)


Recently system-on-chip (SOC) design based on IP cores has become the trend of IC design. To prevent the testing problem from becoming the bottleneck of the cored-based design, the IEEE P1500 Working Group is defining a test standard that can greatly simplify the core test problem. In this paper, we propose a new core-based test architecture that can support the IEEE P1500 cores as well as the well-accepted IEEE 1149.1 cores. Both the serial and parallel testing capabilities are provided. Moreover, a new hierarchical test control mechanism has been developed that facilitates the hierarchical test access for deeply embedded cores.

頁(從 - 到)248-253
期刊Proceedings of the Asian Test Symposium
出版狀態Published - 2000 十二月 1
事件9th Asian Test Symposium - Taipei, Taiwan
持續時間: 2000 十二月 42000 十二月 6


All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering