High-density SRAM voltage scaling enabled by inserted-oxide FinFET technology

Yi Ting Wu, Meng Hsueh Chiang, Jone F. Chen, Fei Ding, Daniel Connelly, Tsu Jae King Liu

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

A scheme to precisely adjust the drive strength of an inserted-oxide FinFET (iFinFET), to enhance the manufacturing yield of a minimally sized six-transistor (6-T) SRAM cell, is proposed. Specifically, the top nanowire (NW) channel in an iFinFET can be made to be essentially non-conducting by ion implantation to increase its threshold voltage, and the position of the inserted-oxide layer can be optimized for maximum cell yield at low operating voltage. Via three-dimensional (3-D) device simulations and a calibrated compact model, this scheme is projected to lower the minimum operating voltage (Vmin) of a minimally sized 6-T SRAM cell.

原文English
主出版物標題2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1-3
頁數3
ISBN(電子)9781538637654
DOIs
出版狀態Published - 2017 7月 2
事件2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 - Burlingame, United States
持續時間: 2017 10月 162017 10月 18

出版系列

名字2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
2018-March

Other

Other2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
國家/地區United States
城市Burlingame
期間17-10-1617-10-18

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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