High gate breakdown voltage and low leakage current using selective citric etchant on the sidewall recessed AlGaAs/InGaAs PHEMTs

K. F. Yarn, C. I. Liao, Yeong-Her Wang, Mau-phon Houng

研究成果: Article

摘要

A novel effective and simple method of selective gate sidewall recess is proposed to expose the low barrier channel at mesa sidewalls during device isolation for Al0.2Ga0.8As/In0.15Ga 0.85As PHEMTs (pseudomorphic high electron mobility transistors) by using a newly developed citric-acid-based etchant with high selectivity (>250) for GaAs/Al0.2Ga0.8As or In 0.15Ga0.85As/Al0.8Ga0.8As interfaces. After sidewall recess, a revealed cavity will exist between the In0.15Gao0.85As layers and gate metals. Devices with 1×100 μm2 typically exhibit a very low gate leakage current of 2.4 μA/mm even at VGD=-10V and high gate breakdown voltage over 25V. In our experiments, the maximum gate breakdown voltages for gate-recessed devices with 1× 100 μm2 and 2×100 μm2 are up to 45V and 38.5V, respectively. As compared to that of non-recessed devices, over three orders of reduction in magnitude of gate leakage currents and over three times of increase in gate breakdown voltages are achieved.

原文English
頁(從 - 到)2707-2712
頁數6
期刊Journal of Optoelectronics and Advanced Materials
7
發行號5
出版狀態Published - 2005 十月 1

    指紋

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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