High gate breakdown voltage and low leakage current using selective citric etchant on the sidewall recessed AlGaAs/InGaAs PHEMTs

A novel effective and simple method of selective gate sidewall recess is proposed to expose the low barrier channel at mesa sidewalls during device isolation for Al_0.2Ga_0.8As/In_0.15Ga _0.85As PHEMTs (pseudomorphic high electron mobility transistors) by using a newly developed citric-acid-based etchant with high selectivity (>250) for GaAs/Al_0.2Ga_0.8As or In _0.15Ga_0.85As/Al_0.8Ga_0.8As interfaces. After sidewall recess, a revealed cavity will exist between the In_0.15Gao_0.85As layers and gate metals. Devices with 1×100 μm² typically exhibit a very low gate leakage current of 2.4 μA/mm even at V_GD=-10V and high gate breakdown voltage over 25V. In our experiments, the maximum gate breakdown voltages for gate-recessed devices with 1× 100 μm² and 2×100 μm² are up to 45V and 38.5V, respectively. As compared to that of non-recessed devices, over three orders of reduction in magnitude of gate leakage currents and over three times of increase in gate breakdown voltages are achieved.