High-performance NTT architecture for large integer multiplication

Jheng Hao Ye, Ming Der Shieh

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

This paper presents an efficient architecture of number Theoretical transform (NTT), targeting at fulfilling large integer multiplication for fully homomorphic encryption applications. A systematic memory management scheme is proposed for the pipelined shared-memory NTT architecture implemented with mixed-radix multi-path delay commutators (MDCs). The presented data relocation scheme along with the MDC can be applied to merge multiple banks with single-port memory for further reducing the area requirement. Experimental results show that a 1,179,648-bit multiplier implemented by the proposed solution, including seamless data transfer among the building blocks, can lead to more than 39.8% area reduction with even a lower computational time as compared with the related works.

原文English
主出版物標題2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1-4
頁數4
ISBN(電子)9781538642603
DOIs
出版狀態Published - 2018 六月 5
事件2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan
持續時間: 2018 四月 162018 四月 19

出版系列

名字2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Other

Other2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
國家/地區Taiwan
城市Hsinchu
期間18-04-1618-04-19

All Science Journal Classification (ASJC) codes

  • 安全、風險、可靠性和品質
  • 控制和優化
  • 硬體和架構
  • 電氣與電子工程

指紋

深入研究「High-performance NTT architecture for large integer multiplication」主題。共同形成了獨特的指紋。

引用此