High-speed C-testable systolic array design for Galois-Field inversion

Chih Tsun Huang, Cheng Wen Wu

研究成果: Conference article同行評審

16 引文 斯高帕斯(Scopus)


Systolic architectures for inversion in Galois field (GF(2m)) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.

頁(從 - 到)342-346
期刊Proceedings of European Design and Test Conference
出版狀態Published - 1997 1月 1
事件Proceedings of the 1997 European Design & Test Conference - Paris, Fr
持續時間: 1997 3月 171997 3月 20

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程


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