Galois field (GF) computation is important in applications such as error-control coding, switching theory, and cryptography. In GF, division and inversion operations are much harder to implement in digital logic as compared with multiplication and addition operations so far as performance and hardware complexity is concerned. Although several VLSI structures for division or inversion have been proposed in the past, most of them have complex routing, nonmodular architectures, and low testability. Testability especially is an increasing concern in VLSI design. In this paper, C-testable bit-level systolic arrays for GF(2m) inversion are presented. We propose a counter-free extended Euclidean algorithm for GF inversion. Based on the algorithm, we obtain efficient systolic GF inverters, which are extendible to GF dividers. Both the bit-parallel and bit-serial inverters proposed are shown to be easily testable. For example, the bit-serial inverter requires only four test patterns regardless of the field size (or number of cells). High testability is a key advantage for the proposed GF inverters, especially in core-based VLSI system chips.
|頁（從 - 到）||909-918|
|期刊||IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing|
|出版狀態||Published - 2000 九月 1|
All Science Journal Classification (ASJC) codes
- Signal Processing
- Electrical and Electronic Engineering