High speed, fine resolution pattern generation using the matched delay technique

Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin

研究成果: Conference article同行評審

摘要

This paper presents an architecture for generating a highspeed data pattern with precise edge placement (resolution) by using the matched delay technique. The technique involves passing clock and data signals through arrays of matched delay elements in such a way that the data rate and resolution of the generated data stream are controlled by the difference of these matched delays. This difference can be made much smaller than an absolute gate delay. Since the resolution of conventional designs is determined by these absolute delays, the matched delay technique yields a much finer resolution as well as higher speeds than traditional methods. The matched delay technique lends itself to high-precision and high-speed applications such as fast network interfaces or test pattern generators. This paper also describes a matched delay data generator submitted for fabrication in a MOSIS 1.2μm CMOS technology. Simulations indicate that data signals with on-chip bit rates of 833Mb/s and resolutions of 100ps can be generated.

原文English
頁(從 - 到)405-408
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
1
出版狀態Published - 1995
事件Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
持續時間: 1995 4月 301995 5月 3

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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