High-speed low-complexity implementation for data weighted averaging algorithm [ΣΔ modulator applications]

Da Huei Lee, Ching Chung Li, Tai Haur Kuo

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

In this paper, a high-speed, low-complexity implementation of a data weighted averaging (DWA) algorithm is presented. Different from other published implementations, the maximum speed-limited function of the DWA algorithm, decoding for control signal generation and adding for register value updating, are replaced by carry look-ahead and rotating. Additionally, register simplification is adopted to reduce area costs. This design, in 0.25 μm CMOS, for a 3-bit 8-element example can operate at a 800 MHz clock rates for post-layout simulations, and costs only 254 transistors.

原文English
主出版物標題2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
頁面283-286
頁數4
ISBN(電子)0780373634, 9780780373631
DOIs
出版狀態Published - 2002 一月 1
事件3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan
持續時間: 2002 八月 62002 八月 8

出版系列

名字2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Other

Other3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
國家Taiwan
城市Taipei
期間02-08-0602-08-08

    指紋

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

引用此

Lee, D. H., Li, C. C., & Kuo, T. H. (2002). High-speed low-complexity implementation for data weighted averaging algorithm [ΣΔ modulator applications]. 於 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings (頁 283-286). [1031587] (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2002.1031587