TY - GEN
T1 - High-speed low-complexity implementation for data weighted averaging algorithm [ΣΔ modulator applications]
AU - Lee, Da Huei
AU - Li, Ching Chung
AU - Kuo, Tai Haur
PY - 2002/1/1
Y1 - 2002/1/1
N2 - In this paper, a high-speed, low-complexity implementation of a data weighted averaging (DWA) algorithm is presented. Different from other published implementations, the maximum speed-limited function of the DWA algorithm, decoding for control signal generation and adding for register value updating, are replaced by carry look-ahead and rotating. Additionally, register simplification is adopted to reduce area costs. This design, in 0.25 μm CMOS, for a 3-bit 8-element example can operate at a 800 MHz clock rates for post-layout simulations, and costs only 254 transistors.
AB - In this paper, a high-speed, low-complexity implementation of a data weighted averaging (DWA) algorithm is presented. Different from other published implementations, the maximum speed-limited function of the DWA algorithm, decoding for control signal generation and adding for register value updating, are replaced by carry look-ahead and rotating. Additionally, register simplification is adopted to reduce area costs. This design, in 0.25 μm CMOS, for a 3-bit 8-element example can operate at a 800 MHz clock rates for post-layout simulations, and costs only 254 transistors.
UR - http://www.scopus.com/inward/record.url?scp=84966417125&partnerID=8YFLogxK
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U2 - 10.1109/APASIC.2002.1031587
DO - 10.1109/APASIC.2002.1031587
M3 - Conference contribution
AN - SCOPUS:84966417125
T3 - 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
SP - 283
EP - 286
BT - 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Y2 - 6 August 2002 through 8 August 2002
ER -