High-speed rail-to-rail output buffer amplifier with dynamic-bias circuit

Chien-Hung Tsai; J. H. Wang; C. T. Chang; C. Y. Wang

doi:10.1049/el.2009.2692

High-speed rail-to-rail output buffer amplifier with dynamic-bias circuit

Chien-Hung Tsai, J. H. Wang, C. T. Chang, C. Y. Wang

電機工程學系

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

摘要

The design of a high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB output stage and auxiliary output stage at the same time. The proposed dynamic bias method not only increases the driving capability of the class-AB output stage but also maintains a small quiescent current path.

原文	English
頁（從 - 到）	1199-1200
頁數	2
期刊	Electronics Letters
卷	45
發行號	24
DOIs	https://doi.org/10.1049/el.2009.2692
出版狀態	Published - 2009 12月 1

All Science Journal Classification (ASJC) codes

電氣與電子工程

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10.1049/el.2009.2692

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引用此

@article{63c4166558b24c759a7617836ad46b91,

title = "High-speed rail-to-rail output buffer amplifier with dynamic-bias circuit",

abstract = "The design of a high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB output stage and auxiliary output stage at the same time. The proposed dynamic bias method not only increases the driving capability of the class-AB output stage but also maintains a small quiescent current path.",

author = "Chien-Hung Tsai and Wang, {J. H.} and Chang, {C. T.} and Wang, {C. Y.}",

year = "2009",

month = dec,

day = "1",

doi = "10.1049/el.2009.2692",

language = "English",

volume = "45",

pages = "1199--1200",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "Institution of Engineering and Technology",

number = "24",

}

TY - JOUR

T1 - High-speed rail-to-rail output buffer amplifier with dynamic-bias circuit

AU - Tsai, Chien-Hung

AU - Wang, J. H.

AU - Chang, C. T.

AU - Wang, C. Y.

PY - 2009/12/1

Y1 - 2009/12/1

N2 - The design of a high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB output stage and auxiliary output stage at the same time. The proposed dynamic bias method not only increases the driving capability of the class-AB output stage but also maintains a small quiescent current path.

AB - The design of a high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB output stage and auxiliary output stage at the same time. The proposed dynamic bias method not only increases the driving capability of the class-AB output stage but also maintains a small quiescent current path.

UR - http://www.scopus.com/inward/record.url?scp=70549101391&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70549101391&partnerID=8YFLogxK

U2 - 10.1049/el.2009.2692

DO - 10.1049/el.2009.2692

M3 - Article

AN - SCOPUS:70549101391

SN - 0013-5194

VL - 45

SP - 1199

EP - 1200

JO - Electronics Letters

JF - Electronics Letters

IS - 24

ER -

High-speed rail-to-rail output buffer amplifier with dynamic-bias circuit

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