High throughput 2-D transform architectures for H.264 advanced video coders

Zhan Yuan Cheng, Che Hong Chen, Bin Da Liu, Jar Ferr Yang

研究成果: Paper

48 引文 (Scopus)

摘要

In this paper, high throughput hardware architectures for fast computation of the 2-D forward, inverse and Hadamard transforms suggested in H.264 advanced video coders (AVC) are presented. After complexity and efficiency analyses, we find that the proposed architectures could provide higher throughput rate and realize in a smaller chip area than the conventional row-column approaches. The proposed architectures are synthesized with TSMC 0.35 μm technology. The synthesized multiple transform architecture could process 800 M samples/sec at 100 MHz for all three transforms.

原文English
頁面1141-1144
頁數4
出版狀態Published - 2004 十二月 1
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
持續時間: 2004 十二月 62004 十二月 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家Taiwan
城市Tainan
期間04-12-0604-12-09

指紋

Throughput
Hadamard transforms
Inverse transforms
Hardware

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

Cheng, Z. Y., Chen, C. H., Liu, B. D., & Yang, J. F. (2004). High throughput 2-D transform architectures for H.264 advanced video coders. 1141-1144. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.
Cheng, Zhan Yuan ; Chen, Che Hong ; Liu, Bin Da ; Yang, Jar Ferr. / High throughput 2-D transform architectures for H.264 advanced video coders. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.4 p.
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Cheng, ZY, Chen, CH, Liu, BD & Yang, JF 2004, 'High throughput 2-D transform architectures for H.264 advanced video coders', 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan, 04-12-06 - 04-12-09 頁 1141-1144.

High throughput 2-D transform architectures for H.264 advanced video coders. / Cheng, Zhan Yuan; Chen, Che Hong; Liu, Bin Da; Yang, Jar Ferr.

2004. 1141-1144 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.

研究成果: Paper

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Cheng ZY, Chen CH, Liu BD, Yang JF. High throughput 2-D transform architectures for H.264 advanced video coders. 2004. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.