High-throughput low-cost VLSI architecture for AVC/H.264 CAVLC decoding

G. G. Lee, C. C. Lo, Y. C. Chen, H. Y. Lin, M. J. Wang

研究成果: Article同行評審

9 引文 斯高帕斯(Scopus)

摘要

This study develops a low-cost very-large-scale-integration (VLSI) hardware architecture for entropy coding with increased throughput using the statistical properties of context-based adaptive variable-length coding (CAVLC) in AVC/H.264. Statistical analyses show that better symbol length prediction was achieved by breaking the recursive dependency among codewords for the multi-symbol decoder implementation. The proposed CAVLC decoder easily meets the real-time requirements for high definition (HD) (1920×1088) applications. The clock speed is only 13 MHz under the best case scenario.

原文English
文章編號IIPEAT000004000002000081000001
頁(從 - 到)81-91
頁數11
期刊IET Image Processing
4
發行號2
DOIs
出版狀態Published - 2010 四月 1

All Science Journal Classification (ASJC) codes

  • Software
  • Signal Processing
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering

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