High-Throughput Reconfigurable Variable Length Coding Decoder for MPEG-2 and AVC/H.264

Gwo Giun (Chris) Lee, Chun Fu Chen, Shu Ming Xu, Ching Jui Hsiao

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)


This paper presents a reconfigurable architecture for two video coding standards, MPEG-2 and AVC/H.264. The proposed reconfigurable architecture dynamically configures the architecture to achieve multiple functions in variable length coding decoder and context-adaptive variable length coding decoder. By means of extracting the commonalities at the low-level dataflow, the designed reconfigurable architecture optimizes hardware resources and increases architectural flexibility through the reconfigurability in the adaptively constructing architecture. On the other hand, the proposed reconfigurable architecture combines several strategies in AVC/H.264 mode, and subsequently revises and integrates these mechanisms to achieve a high-throughput rate. As a consequence, the memory usage of the proposed reconfigurable architecture achieves 37.5 % memory bits saving and 46.7 % memory area reduction as compared to the individual implementation; moreover, in AVC/H.264 mode, this reconfigurable architecture requires only 50 cycles to decode one marcoblock on average. Due to the flexibility, the proposed reconfigurable architecture costs 10.8 K gates by using 0.18 μm CMOS technology at the 108 MHz clock rate, and supports variable length coding in MPEG-2 with 1920 × 1080@30fps and context-adaptive variable length coding in AVC/H.264 with 1920 × 1080@60fps. From the perspectives of architectural costs and supported functions, the proposed architecture surpasses the related works in the state of the art.

頁(從 - 到)27-40
期刊Journal of Signal Processing Systems
出版狀態Published - 2016 1月 1

All Science Journal Classification (ASJC) codes

  • 控制與系統工程
  • 理論電腦科學
  • 訊號處理
  • 資訊系統
  • 建模與模擬
  • 硬體和架構


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