TY - GEN
T1 - How to enable software isolation and boost system performance with sub-block erase over 3D flash memory
AU - Chang, Hsin Yu
AU - Ho, Chien Chung
AU - Chang, Yuan Hao
AU - Chang, Yu Ming
AU - Kuo, Tei Wei
N1 - Funding Information:
This work was supported in part by the Ministry of Science and Technology under grant Nos. 104-2221-E-001-020-MY3, 105-2221- E-001-004-MY2 and 105-2221-E-001-013-MY3.
Publisher Copyright:
© 2016 ACM.
PY - 2016/11/21
Y1 - 2016/11/21
N2 - The write amplification problem deteriorates as the block size of modern flash-memory chips keeps increasing. Without the careful garbage collection, significant live-page copying might even worsen the reliability problem, that is already severe to 3D flash memory. In this work, we propose a sub-block erase design to not only alleviate the write amplification problem by reducing live-page copying but also improve the system reliability with a software isolation strategy. In particular, sub-blocks are carefully allocated to satisfy write requests so as to reduce disturbance by using free or invalid sub-blocks as isolation layers among sub-blocks, without additional hardware cost and capacity loss. A series of experiments were conducted to evaluate the capability of the proposed design. The results show that the proposed design is very effective in improving the system performance by reducing garbage collection overheads and in improving the device reliability/lifetime.
AB - The write amplification problem deteriorates as the block size of modern flash-memory chips keeps increasing. Without the careful garbage collection, significant live-page copying might even worsen the reliability problem, that is already severe to 3D flash memory. In this work, we propose a sub-block erase design to not only alleviate the write amplification problem by reducing live-page copying but also improve the system reliability with a software isolation strategy. In particular, sub-blocks are carefully allocated to satisfy write requests so as to reduce disturbance by using free or invalid sub-blocks as isolation layers among sub-blocks, without additional hardware cost and capacity loss. A series of experiments were conducted to evaluate the capability of the proposed design. The results show that the proposed design is very effective in improving the system performance by reducing garbage collection overheads and in improving the device reliability/lifetime.
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U2 - 10.1145/2968456.2968475
DO - 10.1145/2968456.2968475
M3 - Conference contribution
AN - SCOPUS:84995466958
T3 - 2016 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2016
BT - 2016 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2016
Y2 - 2 October 2016 through 7 October 2016
ER -