Hybrid BIST scheme for multiple heterogeneous embedded memories

Li Ming Denq, Yu Tsao Hsing, Cheng W. Wu

研究成果: Article同行評審

7 引文 斯高帕斯(Scopus)

摘要

Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics.

原文English
頁(從 - 到)64-73
頁數10
期刊IEEE Design and Test of Computers
26
發行號2
DOIs
出版狀態Published - 2009 六月 3

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 軟體
  • 電氣與電子工程

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