Impact of resistance drift on multilevel PCM design

Yi Hsuan Chiu, Yi Bo Liao, Meng-Hsueh Chiang, Chia Long Lin, Wei-Chou Hsu, Pei Chia Chiang, Yen Ya Hsu, Wen Hsing Liu, Shyh Shyuan Sheu, Keng Li Su, Ming Jer Kao, Ming Jinn Tsai

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

Design issues and insights of multilevel phase change memory are presented. Based on a proposed compact model calibrated to measured data, we assess the impact of resistance drift on multilevel cell design. It is found that special care has to be taken to develop a viable multilevel design as the design window could be degraded and worsened at high temperature.

原文English
主出版物標題2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010
頁面20-23
頁數4
DOIs
出版狀態Published - 2010 八月 20
事件2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010 - Grenoble, France
持續時間: 2010 六月 22010 六月 4

出版系列

名字2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010

Other

Other2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010
國家France
城市Grenoble
期間10-06-0210-06-04

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • 引用此

    Chiu, Y. H., Liao, Y. B., Chiang, M-H., Lin, C. L., Hsu, W-C., Chiang, P. C., Hsu, Y. Y., Liu, W. H., Sheu, S. S., Su, K. L., Kao, M. J., & Tsai, M. J. (2010). Impact of resistance drift on multilevel PCM design. 於 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010 (頁 20-23). [5510298] (2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010). https://doi.org/10.1109/ICICDT.2010.5510298