Implementation of channel demodulator for DAB system

Chien Ming Wu, Ming-Der Shieh, Hsin Fu Lo, Min Hsiung Hu

研究成果: Conference article

8 引文 (Scopus)

摘要

This paper describes the VLSI implementation of Fast Fourier Transform (FFT) for the Eureka-147 Digital Audio Broadcasting (DAB) system. We emphasize how to minimize the hardware requirement and efficiently manage the memory to meet the DAB requirement. Implementation results demonstrate the applicability of our work with the characteristics of modular design, consuming less silicon area, and facilitating the extension for high transmission rate applications. The core size of the resulting chip implementation is 2086×1806 μm2 based on the TSMC 0.35 μn 1P4M CMOS process. Performance evaluation reveals that our design for the targeted channel demodulator outperform previous solutions.

原文English
期刊Proceedings - IEEE International Symposium on Circuits and Systems
2
出版狀態Published - 2003 七月 14
事件Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
持續時間: 2003 五月 252003 五月 28

指紋

Digital radio
Demodulators
Fast Fourier transforms
Computer hardware
Data storage equipment
Silicon

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

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Implementation of channel demodulator for DAB system. / Wu, Chien Ming; Shieh, Ming-Der; Lo, Hsin Fu; Hu, Min Hsiung.

於: Proceedings - IEEE International Symposium on Circuits and Systems, 卷 2, 14.07.2003.

研究成果: Conference article

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AU - Hu, Min Hsiung

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AB - This paper describes the VLSI implementation of Fast Fourier Transform (FFT) for the Eureka-147 Digital Audio Broadcasting (DAB) system. We emphasize how to minimize the hardware requirement and efficiently manage the memory to meet the DAB requirement. Implementation results demonstrate the applicability of our work with the characteristics of modular design, consuming less silicon area, and facilitating the extension for high transmission rate applications. The core size of the resulting chip implementation is 2086×1806 μm2 based on the TSMC 0.35 μn 1P4M CMOS process. Performance evaluation reveals that our design for the targeted channel demodulator outperform previous solutions.

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