Improve GPGPU Front-end Efficiency Via Inter-Warp Instruction Sharing

General-purpose GPUs (GPGPUs) leverage thousands of threads per core to attain high throughput. Threads executing the same program are dynamically grouped into SIMD batches known as warps, which exhibit high localities in accessing the instruction cache. Current designs allow warps to access the instruction cache independently in a time-sharing manner, leading to significant fetch redundancies. To address this issue, we introduce Inter-Warp Instruction Sharing, a lightweight yet effective technique to improve GPGPU front-end efficiency. The mechanism incorporates an improved fetch request arbitration algorithm, a fetch filter to prevent redundant fetching, and a modified instruction buffer that broadcasts instructions to all active warps. We show that our approach reduces I-Cache accesses by up to 85%, achieving a geometric mean reduction of 68% without performance degradation.