Improved high-k stacks with chemical oxide interfacial layer by DPN/PNA treatment

A decoupled plasma nitridation (DPN) with post nitridation annealing (PNA) treatment method was introduced to improve the performances of MOS devices with high-k (HK)-last/gate-last integration scheme and chemical oxide interface layer (IL). By introducing N to form HfSiON, it was found that DPN + PNA treatments could provide smaller equivalent oxide thickness (EOT) for both nMOS and pMOS devices. It was also found that we could achieve the best overall device performance for the HK-last/gatelast integration scheme with a chemical oxide IL by introducing nitrogen gas with low percentage content during DPN followed by high temperature PNA.