Improvement of Cu / M1 single damascene performance by optimizing ILD / W-plug CMP integration

C. Y. Ho, C. H. Lien

研究成果: Paper同行評審

摘要

Oxide CMP/W-plug CMP were widely adopted to VLSI integration and planarization in 1990's, then expanded to copper/low K material for sheet resistance, parasitic capacitance and cross-talk reduction. Gradually, the oxide CMP/W-plug CMP are almost replaced by Cu / low-K damascene except ILD process. Although the application of ILD oxide CMP/ contact W-plug CMP has been studied for a long time, it is still a key factor to affect BEOL integrated planarization especially for metal 1 single damascene. In this paper, the planarization issue for circuits region (such as SRAM cell) in adjacency to an open area (such as STI) is investigated. The integrated experimental result indicated that opposite topography trend between ILD oxide CMP and W-plug CMP is observed. This characteristic of opposite CMP topography leads to metal 1 single damascene bridge(as shown in Fig. 1). A integrated optimization of ILD oxide thickness, ILD CMP and contact W- plug CMP processes are proposed to resolve M1 IMD planarization issue that is the root cause to induce short of metal 1 single damascene.

原文English
頁面390-392
頁數3
出版狀態Published - 2005 12月 1
事件22nd International VLSI Multilevel Interconnection Conference, VMIC 2005 - Fremont, CA, United States
持續時間: 2005 10月 42005 10月 6

Conference

Conference22nd International VLSI Multilevel Interconnection Conference, VMIC 2005
國家/地區United States
城市Fremont, CA
期間05-10-0405-10-06

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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