Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology

Chan Yuan Hu, Jone F. Chen, Shih Chih Chen, Shoou Jinn Chang, Kay Ming Lee, Chih Ping Lee

研究成果: Article

摘要

An incremental poly etching method can improve the poly pimple defect-induced device mismatch on the static noise margin (SNM) of 65-nm-node low-power 6T-SRAM. The improvement on circuit level is examined by the yield of scan chain and memory built-in self-test (MBIST), which is known to correlate well to process-induced defects.

原文English
文章編號5418971
頁（從 - 到）956-959
頁數4
期刊IEEE Transactions on Electron Devices
卷57
發行號4
DOIs
出版狀態Published - 2010 四月 1

指紋

Static random access storage
Defects
Built-in self test
Etching
Data storage equipment
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此文

Hu, Chan Yuan ; Chen, Jone F. ; Chen, Shih Chih ; Chang, Shoou Jinn ; Lee, Kay Ming ; Lee, Chih Ping. / Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology. 於: IEEE Transactions on Electron Devices. 2010 ; 卷 57, 編號 4. 頁 956-959.
@article{5307c1049687404191640cdfc3eda17f,
title = "Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology",
abstract = "An incremental poly etching method can improve the poly pimple defect-induced device mismatch on the static noise margin (SNM) of 65-nm-node low-power 6T-SRAM. The improvement on circuit level is examined by the yield of scan chain and memory built-in self-test (MBIST), which is known to correlate well to process-induced defects.",
author = "Hu, {Chan Yuan} and Chen, {Jone F.} and Chen, {Shih Chih} and Chang, {Shoou Jinn} and Lee, {Kay Ming} and Lee, {Chih Ping}",
year = "2010",
month = "4",
day = "1",
doi = "10.1109/TED.2010.2041285",
language = "English",
volume = "57",
pages = "956--959",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

Hu, CY, Chen, JF, Chen, SC, Chang, SJ, Lee, KM & Lee, CP 2010, 'Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology', IEEE Transactions on Electron Devices, 卷 57, 編號 4, 5418971, 頁 956-959. https://doi.org/10.1109/TED.2010.2041285

Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology. / Hu, Chan Yuan; Chen, Jone F.; Chen, Shih Chih; Chang, Shoou Jinn; Lee, Kay Ming; Lee, Chih Ping.

於: IEEE Transactions on Electron Devices, 卷 57, 編號 4, 5418971, 01.04.2010, p. 956-959.

研究成果: Article

TY - JOUR

T1 - Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology

AU - Hu, Chan Yuan

AU - Chen, Jone F.

AU - Chen, Shih Chih

AU - Chang, Shoou Jinn

AU - Lee, Kay Ming

AU - Lee, Chih Ping

PY - 2010/4/1

Y1 - 2010/4/1

N2 - An incremental poly etching method can improve the poly pimple defect-induced device mismatch on the static noise margin (SNM) of 65-nm-node low-power 6T-SRAM. The improvement on circuit level is examined by the yield of scan chain and memory built-in self-test (MBIST), which is known to correlate well to process-induced defects.

AB - An incremental poly etching method can improve the poly pimple defect-induced device mismatch on the static noise margin (SNM) of 65-nm-node low-power 6T-SRAM. The improvement on circuit level is examined by the yield of scan chain and memory built-in self-test (MBIST), which is known to correlate well to process-induced defects.

UR - http://www.scopus.com/inward/record.url?scp=77950300736&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77950300736&partnerID=8YFLogxK

U2 - 10.1109/TED.2010.2041285

DO - 10.1109/TED.2010.2041285

M3 - Article

AN - SCOPUS:77950300736

VL - 57

SP - 956

EP - 959

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 4

M1 - 5418971

ER -

Hu CY, Chen JF, Chen SC, Chang SJ, Lee KM, Lee CP. Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology. IEEE Transactions on Electron Devices. 2010 4月 1;57(4):956-959. 5418971. https://doi.org/10.1109/TED.2010.2041285

存取文件