Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology

Chan Yuan Hu; Jone F. Chen; Shih Chih Chen; Shoou Jinn Chang; Kay Ming Lee; Chih Ping Lee

doi:10.1109/TED.2010.2041285

Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology

Chan Yuan Hu, Jone F. Chen, Shih Chih Chen, Shoou Jinn Chang, Kay Ming Lee, Chih Ping Lee

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

摘要

An incremental poly etching method can improve the poly pimple defect-induced device mismatch on the static noise margin (SNM) of 65-nm-node low-power 6T-SRAM. The improvement on circuit level is examined by the yield of scan chain and memory built-in self-test (MBIST), which is known to correlate well to process-induced defects.

原文	English
文章編號	5418971
頁（從 - 到）	956-959
頁數	4
期刊	IEEE Transactions on Electron Devices
卷	57
發行號	4
DOIs	https://doi.org/10.1109/TED.2010.2041285
出版狀態	Published - 2010 4月

All Science Journal Classification (ASJC) codes

電子、光磁材料
電氣與電子工程

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10.1109/TED.2010.2041285

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@article{5307c1049687404191640cdfc3eda17f,

title = "Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology",

abstract = "An incremental poly etching method can improve the poly pimple defect-induced device mismatch on the static noise margin (SNM) of 65-nm-node low-power 6T-SRAM. The improvement on circuit level is examined by the yield of scan chain and memory built-in self-test (MBIST), which is known to correlate well to process-induced defects.",

author = "Hu, {Chan Yuan} and Chen, {Jone F.} and Chen, {Shih Chih} and Chang, {Shoou Jinn} and Lee, {Kay Ming} and Lee, {Chih Ping}",

year = "2010",

month = apr,

doi = "10.1109/TED.2010.2041285",

language = "English",

volume = "57",

pages = "956--959",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology

AU - Hu, Chan Yuan

AU - Chen, Jone F.

AU - Chen, Shih Chih

AU - Chang, Shoou Jinn

AU - Lee, Kay Ming

AU - Lee, Chih Ping

PY - 2010/4

Y1 - 2010/4

N2 - An incremental poly etching method can improve the poly pimple defect-induced device mismatch on the static noise margin (SNM) of 65-nm-node low-power 6T-SRAM. The improvement on circuit level is examined by the yield of scan chain and memory built-in self-test (MBIST), which is known to correlate well to process-induced defects.

AB - An incremental poly etching method can improve the poly pimple defect-induced device mismatch on the static noise margin (SNM) of 65-nm-node low-power 6T-SRAM. The improvement on circuit level is examined by the yield of scan chain and memory built-in self-test (MBIST), which is known to correlate well to process-induced defects.

UR - http://www.scopus.com/inward/record.url?scp=77950300736&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77950300736&partnerID=8YFLogxK

U2 - 10.1109/TED.2010.2041285

DO - 10.1109/TED.2010.2041285

M3 - Article

AN - SCOPUS:77950300736

SN - 0018-9383

VL - 57

SP - 956

EP - 959

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 4

M1 - 5418971

ER -

Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology

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