Improving scalability and complexity of dynamic scheduler through wakeup-based scheduling

Kuo Su Hsiao, Chung-Ho Chen

研究成果: Paper

1 引文 (Scopus)

摘要

This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction scheduler comes with poor scalability and high complexity due to the inefficient and costly instruction wakeup operation. From simulation-based analyses, we find that 98% of the wakeup activities are useless in the conventional wakeup logic. These useless activities consume a lot of power and slowdown the scheduling speed. To address this problem, the proposed technique schedules the instructions into the segmented issue window based on their wakeup addresses. During the wakeup process, the wakeup operation is only performed in the segment selected by the wakeup address of the result tag. The other segments are excluded from the wakeup operation to reduce the useless wakeup activities. The experimental results show that the proposed technique saves 50-61% of the power consumption, reduces 42-76% in the wakeup latency compared to the conventional design.

原文English
頁面197-202
頁數6
DOIs
出版狀態Published - 2006 十二月 1
事件24th International Conference on Computer Design 2006, ICCD - San Jose, CA, United States
持續時間: 2006 十月 12006 十月 4

Other

Other24th International Conference on Computer Design 2006, ICCD
國家United States
城市San Jose, CA
期間06-10-0106-10-04

指紋

Scalability
Scheduling
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Computer Graphics and Computer-Aided Design
  • Software

引用此文

Hsiao, K. S., & Chen, C-H. (2006). Improving scalability and complexity of dynamic scheduler through wakeup-based scheduling. 197-202. 論文發表於 24th International Conference on Computer Design 2006, ICCD, San Jose, CA, United States. https://doi.org/10.1109/ICCD.2006.4380817
Hsiao, Kuo Su ; Chen, Chung-Ho. / Improving scalability and complexity of dynamic scheduler through wakeup-based scheduling. 論文發表於 24th International Conference on Computer Design 2006, ICCD, San Jose, CA, United States.6 p.
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abstract = "This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction scheduler comes with poor scalability and high complexity due to the inefficient and costly instruction wakeup operation. From simulation-based analyses, we find that 98{\%} of the wakeup activities are useless in the conventional wakeup logic. These useless activities consume a lot of power and slowdown the scheduling speed. To address this problem, the proposed technique schedules the instructions into the segmented issue window based on their wakeup addresses. During the wakeup process, the wakeup operation is only performed in the segment selected by the wakeup address of the result tag. The other segments are excluded from the wakeup operation to reduce the useless wakeup activities. The experimental results show that the proposed technique saves 50-61{\%} of the power consumption, reduces 42-76{\%} in the wakeup latency compared to the conventional design.",
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Hsiao, KS & Chen, C-H 2006, 'Improving scalability and complexity of dynamic scheduler through wakeup-based scheduling', 論文發表於 24th International Conference on Computer Design 2006, ICCD, San Jose, CA, United States, 06-10-01 - 06-10-04 頁 197-202. https://doi.org/10.1109/ICCD.2006.4380817

Improving scalability and complexity of dynamic scheduler through wakeup-based scheduling. / Hsiao, Kuo Su; Chen, Chung-Ho.

2006. 197-202 論文發表於 24th International Conference on Computer Design 2006, ICCD, San Jose, CA, United States.

研究成果: Paper

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N2 - This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction scheduler comes with poor scalability and high complexity due to the inefficient and costly instruction wakeup operation. From simulation-based analyses, we find that 98% of the wakeup activities are useless in the conventional wakeup logic. These useless activities consume a lot of power and slowdown the scheduling speed. To address this problem, the proposed technique schedules the instructions into the segmented issue window based on their wakeup addresses. During the wakeup process, the wakeup operation is only performed in the segment selected by the wakeup address of the result tag. The other segments are excluded from the wakeup operation to reduce the useless wakeup activities. The experimental results show that the proposed technique saves 50-61% of the power consumption, reduces 42-76% in the wakeup latency compared to the conventional design.

AB - This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction scheduler comes with poor scalability and high complexity due to the inefficient and costly instruction wakeup operation. From simulation-based analyses, we find that 98% of the wakeup activities are useless in the conventional wakeup logic. These useless activities consume a lot of power and slowdown the scheduling speed. To address this problem, the proposed technique schedules the instructions into the segmented issue window based on their wakeup addresses. During the wakeup process, the wakeup operation is only performed in the segment selected by the wakeup address of the result tag. The other segments are excluded from the wakeup operation to reduce the useless wakeup activities. The experimental results show that the proposed technique saves 50-61% of the power consumption, reduces 42-76% in the wakeup latency compared to the conventional design.

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Hsiao KS, Chen C-H. Improving scalability and complexity of dynamic scheduler through wakeup-based scheduling. 2006. 論文發表於 24th International Conference on Computer Design 2006, ICCD, San Jose, CA, United States. https://doi.org/10.1109/ICCD.2006.4380817