This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction scheduler comes with poor scalability and high complexity due to the inefficient and costly instruction wakeup operation. From simulation-based analyses, we find that 98% of the wakeup activities are useless in the conventional wakeup logic. These useless activities consume a lot of power and slowdown the scheduling speed. To address this problem, the proposed technique schedules the instructions into the segmented issue window based on their wakeup addresses. During the wakeup process, the wakeup operation is only performed in the segment selected by the wakeup address of the result tag. The other segments are excluded from the wakeup operation to reduce the useless wakeup activities. The experimental results show that the proposed technique saves 50-61% of the power consumption, reduces 42-76% in the wakeup latency compared to the conventional design.
|出版狀態||Published - 2006 12月 1|
|事件||24th International Conference on Computer Design 2006, ICCD - San Jose, CA, United States|
持續時間: 2006 10月 1 → 2006 10月 4
|Other||24th International Conference on Computer Design 2006, ICCD|
|城市||San Jose, CA|
|期間||06-10-01 → 06-10-04|
All Science Journal Classification (ASJC) codes