TY - JOUR
T1 - Infection-based dead page prediction in hybrid memory architecture
AU - Lin, Ing Chao
AU - Chang, Da Wei
AU - Kao, Chen Tai
AU - Lin, Sheng Xuan
N1 - Funding Information:
Manuscript received November 6, 2018; revised April 21, 2019; accepted May 21, 2019. Date of publication July 12, 2019; date of current version September 25, 2019. This work was supported in part by the Ministry of Science and Technology of Taiwan under Grant MOST 106-2221-E-006-027-MY3 and Grant MOST 107-2221-E-006-044-MY3 and in part by the Industrial Technology Research Institute of Taiwan under Grant 52-B0-201503-01, Grant B5-10412-HQ-02, and Grant B5-10512-HQ-03. (Corresponding author: Ing-Chao Lin.) The authors are with the Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan 701, Taiwan (email: [email protected]; [email protected]; kaosai324@ gmail.com; [email protected]).
Publisher Copyright:
© 1993-2012 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - With the widespread use of cloud computing and the Internet, applications that require a large memory footprint, such as in-memory databases, have gained in popularity. These applications depend on a high capacity, reliable memory architecture. To achieve these two goals, hybrid memory that uses both DRAM and nonvolatile memory (NVM) provides benefits that include large capacity and nonvolatility. However, NVM is usually accompanied by high write latency and endurance problems. It is important to reduce NVM writes and improve the latency and lifetime of hybrid memory. One way to reduce NVM writes is to reduce dead pages that occupy DRAM and have not been accessed for a long time. When dead pages are removed from the memory, more space can be reserved for frequently accessed data, reducing DRAM misses and NVM writes. Currently, there are several dead block prediction techniques that can identify dead blocks and reduce miss rates at the cache level. However, they are not effective at the memory level because CPU memory accesses exhibit less locality when accesses are filtered by caches. To propose an application that is suitable at the memory level and to achieve a reduction in NVM writes, this paper proposes a simple but effective dead page predictor, called the infection-based dead page predictor (IDP), for the memory level. IDP uses the access counts of evicted pages to determine if nearby pages are also dead pages (i.e., other pages are infected by evicted pages). The simulation results show that compared to related work, the proposed predictor significantly reduces DRAM misses and enhances lifetime.
AB - With the widespread use of cloud computing and the Internet, applications that require a large memory footprint, such as in-memory databases, have gained in popularity. These applications depend on a high capacity, reliable memory architecture. To achieve these two goals, hybrid memory that uses both DRAM and nonvolatile memory (NVM) provides benefits that include large capacity and nonvolatility. However, NVM is usually accompanied by high write latency and endurance problems. It is important to reduce NVM writes and improve the latency and lifetime of hybrid memory. One way to reduce NVM writes is to reduce dead pages that occupy DRAM and have not been accessed for a long time. When dead pages are removed from the memory, more space can be reserved for frequently accessed data, reducing DRAM misses and NVM writes. Currently, there are several dead block prediction techniques that can identify dead blocks and reduce miss rates at the cache level. However, they are not effective at the memory level because CPU memory accesses exhibit less locality when accesses are filtered by caches. To propose an application that is suitable at the memory level and to achieve a reduction in NVM writes, this paper proposes a simple but effective dead page predictor, called the infection-based dead page predictor (IDP), for the memory level. IDP uses the access counts of evicted pages to determine if nearby pages are also dead pages (i.e., other pages are infected by evicted pages). The simulation results show that compared to related work, the proposed predictor significantly reduces DRAM misses and enhances lifetime.
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U2 - 10.1109/TVLSI.2019.2922660
DO - 10.1109/TVLSI.2019.2922660
M3 - Article
AN - SCOPUS:85077712746
SN - 1063-8210
VL - 27
SP - 2401
EP - 2412
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 10
M1 - 8760526
ER -