@inproceedings{1ff0a4f7b2bb40509634e8987bc3b4da,
title = "Insight into Latchup Risk in 28nm Planar Bulk Technology for Quantum Computing Applications",
abstract = "In this work, impact of cryogenic operation temperatures on latchup in 28nm planar bulk CMOS technology is discussed for quantum computing applications. Measurement and simulation results indicate that at low temperatures the sheet well resistances experiences 60\% increase. Further simulations reveal that the vertical resistance increases leading to latchup risk. However, the current gain product of the parasitic bipolar transistors reduces, and holing voltage is increased with low temperatures which can compensate the latchup risk.",
author = "Kateryna Serbulova and Qiu, \{Zi En\} and Chen, \{Shih Hung\} and Alexander Grill and Kao, \{Kuo Hsing\} and \{De Boeck\}, Jo and Guido Groeseneken",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 IEEE International Reliability Physics Symposium, IRPS 2024 ; Conference date: 14-04-2024 Through 18-04-2024",
year = "2024",
doi = "10.1109/IRPS48228.2024.10529388",
language = "English",
series = "IEEE International Reliability Physics Symposium Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2024 IEEE International Reliability Physics Symposium, IRPS 2024 - Proceedings",
address = "United States",
}