Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs

Ming Yu Chang, Li Jing Wang, Meng-Hsueh Chiang

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

摘要

This work investigates the scaling impact on the feasibility of back-gate biasing for ultra-thin-body and BOX fully depleted SOI MOSFETs (UTBB FD SOI) at 5nm technology node. Though the effectiveness of the threshold voltage (Vt) modulation by back bias is limited due to bulk inversion as a result of silicon film scaling, such an issue of reduced Vt window can be relieved by decreasing BOX thickness as the back-gate coupling could be enhanced by thin-BOX-reduced inversion charge centroid in scaled SOI film.

原文English
主出版物標題2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781538676264
DOIs
出版狀態Published - 2019 2月 11
事件2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 - Burlingame, United States
持續時間: 2018 10月 152018 10月 18

出版系列

名字2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018

Conference

Conference2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
國家/地區United States
城市Burlingame
期間18-10-1518-10-18

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程
  • 安全、風險、可靠性和品質
  • 電子、光磁材料
  • 儀器

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