Interconnect reliability modeling for lead-free fan-out chip scale package

Yu Ren Chen, G. S. Shen, Hung Chun Yang, Tz Cheng Chiu

研究成果: Conference contribution

7 引文 斯高帕斯(Scopus)

摘要

The fan-out-type chip scale package (fan-out CSP) is an embedded chip packaging technology that eliminates the need for wirebond and flip-chip bumps. In this study, the board-level reliability of fanout CSP is studied by using three-dimensional finite element analysis. A design of simulations study is applied to investigate the influences of package geometry on the board-level interconnect reliability of fan-out CSP. Results of the analysis ndicate that better board-level reliability for the fan-out CSP can be achieved by using a thicker di with thinner molding compound. In addition, the response surface model obtained from the design of simulations study can be served a the basis for further fan-out CSP design optimization.

原文English
主出版物標題2008 10th International Conference on Electronic Materials and Packaging, EMAP 2008
頁面115-119
頁數5
DOIs
出版狀態Published - 2008
事件2008 10th International Conference on Electronic Materials and Packaging, EMAP 2008 - Taipei, Taiwan
持續時間: 2008 十月 222008 十月 24

出版系列

名字2008 10th International Conference on Electronic Materials and Packaging, EMAP 2008

Other

Other2008 10th International Conference on Electronic Materials and Packaging, EMAP 2008
國家/地區Taiwan
城市Taipei
期間08-10-2208-10-24

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程
  • 機械工業

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