Inverter logic of AlGaAs/InGaAs enhancement/depletion-mode pseudomorphic high electron mobility transistors with virtual channel layers

Jung Hui Tsai, Pao Sheng Lin, Wen Shiung Lour, Wen Chau Liu

研究成果: Article

摘要

In this article, the direct-coupled FET logic (DCFL) inverters are implemented by co-integrated AlGaAs/InGaAs depletion-mode and enhancement-mode pseudomorphic high electron mobility transistors with virtual channel layers, and the inverters with varying gate width of the depletion-mode transistors are demonstrated. The experimental results show that the drain current IDS (mA/mm) and gm (mS/mm) per unit gate width increases as the gate widths of the depletion-mode devices decrease. This is attributed to the fact that the drain current and transconductance values are related to the channel-to-source resistance and the source contact resistance. When the gate width is reduced, the source pad contact area is only slightly changed and the IDS (mA/mm) as well as the transconductance gm (mS/mm) will increase. In addition, it is also observed that for the reduce of the gate width of the depletion-mode devices, the transfer characteristics of the DCFL inverters are steep and shift to the left due to the smaller drain saturation current of the load transistor.

原文English
頁(從 - 到)Q211-Q216
期刊ECS Journal of Solid State Science and Technology
8
發行號10
DOIs
出版狀態Published - 2019 一月 1

指紋

Drain current
Transconductance
High electron mobility transistors
Field effect transistors
Transistors
Contact resistance

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials

引用此文

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title = "Inverter logic of AlGaAs/InGaAs enhancement/depletion-mode pseudomorphic high electron mobility transistors with virtual channel layers",
abstract = "In this article, the direct-coupled FET logic (DCFL) inverters are implemented by co-integrated AlGaAs/InGaAs depletion-mode and enhancement-mode pseudomorphic high electron mobility transistors with virtual channel layers, and the inverters with varying gate width of the depletion-mode transistors are demonstrated. The experimental results show that the drain current IDS (mA/mm) and gm (mS/mm) per unit gate width increases as the gate widths of the depletion-mode devices decrease. This is attributed to the fact that the drain current and transconductance values are related to the channel-to-source resistance and the source contact resistance. When the gate width is reduced, the source pad contact area is only slightly changed and the IDS (mA/mm) as well as the transconductance gm (mS/mm) will increase. In addition, it is also observed that for the reduce of the gate width of the depletion-mode devices, the transfer characteristics of the DCFL inverters are steep and shift to the left due to the smaller drain saturation current of the load transistor.",
author = "Tsai, {Jung Hui} and Lin, {Pao Sheng} and Lour, {Wen Shiung} and Liu, {Wen Chau}",
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AU - Tsai, Jung Hui

AU - Lin, Pao Sheng

AU - Lour, Wen Shiung

AU - Liu, Wen Chau

PY - 2019/1/1

Y1 - 2019/1/1

N2 - In this article, the direct-coupled FET logic (DCFL) inverters are implemented by co-integrated AlGaAs/InGaAs depletion-mode and enhancement-mode pseudomorphic high electron mobility transistors with virtual channel layers, and the inverters with varying gate width of the depletion-mode transistors are demonstrated. The experimental results show that the drain current IDS (mA/mm) and gm (mS/mm) per unit gate width increases as the gate widths of the depletion-mode devices decrease. This is attributed to the fact that the drain current and transconductance values are related to the channel-to-source resistance and the source contact resistance. When the gate width is reduced, the source pad contact area is only slightly changed and the IDS (mA/mm) as well as the transconductance gm (mS/mm) will increase. In addition, it is also observed that for the reduce of the gate width of the depletion-mode devices, the transfer characteristics of the DCFL inverters are steep and shift to the left due to the smaller drain saturation current of the load transistor.

AB - In this article, the direct-coupled FET logic (DCFL) inverters are implemented by co-integrated AlGaAs/InGaAs depletion-mode and enhancement-mode pseudomorphic high electron mobility transistors with virtual channel layers, and the inverters with varying gate width of the depletion-mode transistors are demonstrated. The experimental results show that the drain current IDS (mA/mm) and gm (mS/mm) per unit gate width increases as the gate widths of the depletion-mode devices decrease. This is attributed to the fact that the drain current and transconductance values are related to the channel-to-source resistance and the source contact resistance. When the gate width is reduced, the source pad contact area is only slightly changed and the IDS (mA/mm) as well as the transconductance gm (mS/mm) will increase. In addition, it is also observed that for the reduce of the gate width of the depletion-mode devices, the transfer characteristics of the DCFL inverters are steep and shift to the left due to the smaller drain saturation current of the load transistor.

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