Investigation of step-doped channel heterostructure field-effect transistor

L. W. Laih, J. H. Tsai, C. Z. Wu, S. Y. Cheng, W. C. Liu

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

A new heterostructure field-effect transistor (FET) with an InGaAs step-doped-channel (SDC) profile has been fabricated and demonstrated. The SDCFET studied provides the advantages of high current density, high breakdown voltage, wide gate voltage swing for high transconductance, and adjustable threshold voltage. A simple model is employed to analyse the performance of threshold voltage. For comparison two kinds of SDCFETs have been fabricated. For the 1 × 100μm2 gated dimension, maximum drain saturation currents of 735 and 675 mA/mm, maximum transconductances of 200 and 232mS/mm, gate breakdown voltages of 15 and 12V, wide gate voltage swing of 3.3 and 2.6V with transconductance gm higher than 150mS/ mm, and threshold voltage -3.7 and -1.8V are obtained, respectively. These good performance figures show the SDCFET has good potential for high-speed, high-power circuit applications.

原文English
頁(從 - 到)309-312
頁數4
期刊IEE Proceedings: Circuits, Devices and Systems
144
發行號5
DOIs
出版狀態Published - 1997

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

指紋

深入研究「Investigation of step-doped channel heterostructure field-effect transistor」主題。共同形成了獨特的指紋。

引用此