Investigation of Various Bumps and Redistribution Lines to Inhibit Protected Silicon Nitride Cracks in High Pattern Density Chip Package

Ching Yuan Ho, Hsin Cheng, Yuan Chih Chang, Hwa-Teng Lee

研究成果: Article同行評審

摘要

Mechanical stress related to chip packaging failure is the most common reliability issue in semiconductor devices, especially for high pattern density of very-large-scale integration. In this paper, redistribution lines (RDL) corresponding to gold and copper materials with capped layers (Sn-Ag and Au-Ni) were evaluated to investigate the structure dependency on the mechanical properties of intermetallic compounds, and to provide a solution to improve chip package reliability in regard to protect Si3N4 cracks. The simulation results revealed that a thicker Si3N4 film combined with the corner rounding of bump/RDL structures could mitigate Si3N4 film cracks. Voids induced by the fine pitch configuration of the top Al increase the potential risk of Si3N4 cracks during chip packaging. The reflow temperature is a major factor increasing the thermal stress in RDL patterns rather than from the bump structure. A high temperature storage test applied to the Cu pillar/Sn-Ag capping was used to investigate the intermetallic compound growth, shear strength, and hardness.

原文English
頁(從 - 到)5613-5621
頁數9
期刊Journal of Electronic Materials
49
發行號9
DOIs
出版狀態Published - 2020 九月 1

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 凝聚態物理學
  • 電氣與電子工程
  • 材料化學

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