Investigation on single pulse avalanche failure of SiC MOSFET and Si IGBT

Na Ren, Hao Hu, Xiaofeng Lyu, Jiupeng Wu, Hongyi Xu, Ruigang Li, Zheng Zuo, Kang Wang, Kuang Sheng

研究成果: Article同行評審

29 引文 斯高帕斯(Scopus)


In this work, avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) test are investigated and compared with Si IGBT. The experimental results show that SiC MOSFET can handle ∼20% higher avalanche energy at the same current density, and ∼50% higher current density at the same amount of energy. As SiC device has 5× smaller chip size, the advantage will disappear when comparison is performed with avalanche current. To improve the avalanche current capability of SiC MOSFET, failure mechanisms are analyzed. At first, the junction temperature is calculated with V-T model and thermal model, from which a linear dependence of temperature on avalanche current is revealed. Then, the probability of parasitic BJT turn-on is modeled analytically with the base-to-emitter resistance/voltage, which is found to be highly dependent on the p+ ohmic contact resistance (ρc) and base doping concentration (NB) designs of the device. Based on the modeling results, at the peak junction temperature 650 K in UIS test, the BJT turn-on can already be triggered for SiC MOSFET. The failure trigger temperature can be raised with a higher NB and lower ρc design, thus the avalanche current capability can be increased accordingly. On the other hand, with a much deeper p+ body structure design, the Si IGBT can prevent the BJT latch-up failure. Based on the failure analysis, a trench source structure of SiC MOSFET is proposed to further improve the avalanche capability for smaller chip size design.

頁(從 - 到)33-40
期刊Solid-State Electronics
出版狀態Published - 2019 2月

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 凝聚態物理學
  • 電氣與電子工程
  • 材料化學


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