iScan: Indirect-access scan test over HOY test platform

Chao Wen Tzeng, Chun Yen Lin, Shi Yu Huang, Chih Tsun Huang, Jing Jia Liou, Hsi Pin Ma, Po Chiun Huang, Cheng Wen Wu

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

In this paper, we introduce a new test paradigm called indirect-access scan test, demonstrated over the HOY test platform [12]. Unlike the traditional ATE-based testing, the test data in this paradigm are sent to the chip under test via packets over a single indirect channel. Although there is extra test time overhead for establishing the store-and-forward communication, it offers almost unlimited test memory - a highly desirable property since the large volume of test data today could easily blow up a traditional ATE's test memory. In addition to demonstrating the feasibility of this new paradigm, we also show that its efficiency can be substantially improved by two schemes; i.e., primary input (PI) data encoding and dynamic packet formatting. For a design with 155K gates, the speed-up achieved can be more than 50X.

原文English
主出版物標題2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
頁面60-63
頁數4
DOIs
出版狀態Published - 2009 十二月 1
事件2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
持續時間: 2009 四月 282009 四月 30

出版系列

名字2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Other

Other2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
國家/地區Taiwan
城市Hsinchu
期間09-04-2809-04-30

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 控制與系統工程
  • 電氣與電子工程

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