K-band, low-power CMOS injection-locked divide-by-three circuit using shunt-peaking and current-bleeding techniques

Pei Kang Tsai, Chih Yu Liu, Tzuen-Hsi Huang, Janne Wha Wu

研究成果: Article

2 引文 斯高帕斯(Scopus)

摘要

A CMOS divide-by-three injection-locked frequency divider having a wide input locking range of 23-27 GHz is proposed. The wide locking range is achieved by combining the shunt-peaking and current-bleeding techniques. The proposed circuit is fabricated using a 0.18-μm RF CMOS process, and the measured operation range (i.e., total locking range) is 4.32 GHz (from 23.17 to 27.49 GHz) for an input injection power of +4 dBm. The power consumption is 4.28 mW at a supply voltage of 1.2 V. The second-and third-order harmonic suppressions are 38.05 and 37.89 dBc, respectively, for a divided output frequency of 8.4 GHz. The output phase noise under lock at an offset of 1 MHz with an input injection power of +4 dBm is-139 dBc/Hz.

原文English
頁(從 - 到)577-579
頁數3
期刊Microwave and Optical Technology Letters
54
發行號3
DOIs
出版狀態Published - 2012 三月 1

    指紋

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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