@inproceedings{52e93870bfa244d0a05f42678ac714ac,
title = "Kernel Aware Warp Scheduler",
abstract = "Observing that thread blocks of different kernels that use different functional units should be sent to the same SM (Streaming Multiprocessor) to promote the utilization of functional units, we propose a kernel-aware warp scheduler for GPGPUs. The proposed Kernel Aware Warp Scheduler uses the profiling information of the executed kernels to issue instructions from the right warp. The experimental results based on our HSAIL simulation platform show that the overall performance of the kernel execution improves by about 20% on average. The speedup comes from the increased utilization of functional units and effectiveness in hiding of the memory latency due to the proposed warp scheduling policy.",
author = "Tsai, {Sen Chih} and Su, {Yu Xiang} and Chin, {Yu Han} and Ceng, {Wei Zhong} and Chen, {Chung Ho}",
note = "Funding Information: ACKNOWLEDGMENT This work was supported in part by the Ministry of Science and Technology, Taiwan, under Grant MOST 105-2218-E-006-024. The work of GPU memory sub-system architectures was in part supported by the Industrial Technology Research Institute. Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",
year = "2018",
month = apr,
day = "26",
doi = "10.1109/ISCAS.2018.8351552",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings",
address = "United States",
}