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Layout compaction with minimized delay bound on timing critical paths

  • Lih Yang Wang
  • , Yen Tai Lai
  • , Bin Da Liu
  • , Tin Chung Chang

研究成果: Conference contribution

6   連結會在新分頁中開啟 引文 斯高帕斯(Scopus)

摘要

A layout compaction problem which aims at both the performance improvement and area reduction is studied. A new algorithm which first determines the minimal delay bound for performance critical paths and then minimizes the layout size without affecting the previous consideration is proposed. These two steps are formulated as two linear programs and solved by the simplex algorithm. Effective graph-based techniques for finding the initial solution and reducing the problem dimension are employed to reduce the execution time.

原文English
主出版物標題Proceedings - IEEE International Symposium on Circuits and Systems
發行者Publ by IEEE
頁面1849-1852
頁數4
ISBN(列印)0780312813
出版狀態Published - 1993
事件Proceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA
持續時間: 1993 5月 31993 5月 6

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
3
ISSN(列印)0271-4310

Other

OtherProceedings of the 1993 IEEE International Symposium on Circuits and Systems
城市Chicago, IL, USA
期間93-05-0393-05-06

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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