Leakage and aging optimization using transmission gate-based technique

Ing Chao Lin, Chin Hong Lin, Kuan Hui Li

研究成果: Article同行評審

31 引文 斯高帕斯(Scopus)


Negative bias temperature instability (NBTI), which can degrade the switching speed of PMOS transistors, has become a major reliability challenge. Reducing leakage consumption is one of the major design goals. The gate replacement (GR) technique is an effective way to reduce both the NBTI effect and leakage. This technique, however, has less flexibility because the replaced gate can only produce one output value and careful algorithms are needed to decide the output value of the replaced gate. In this paper, we propose a novel transmission gate-based technique to minimize NBTI-induced degradation and leakage. This technique, which can offer logic 1 for NBTI mitigation and logic 0 for leakage reduction, provides higher flexibility, as compared to the GR technique. Simulation results show that our proposed technique has up to 20× and 2.16×, on average, improvement on NBTI-induced degradation with comparable leakage power reduction. With a 19.19% area penalty, combining our technique and the GR can reduce 17.92% of the total leakage power and 32.36% of NBTI-induced circuit degradation.

頁(從 - 到)87-99
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
出版狀態Published - 2013 1月 10

All Science Journal Classification (ASJC) codes

  • 軟體
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程


深入研究「Leakage and aging optimization using transmission gate-based technique」主題。共同形成了獨特的指紋。