In this paper, a novel logic gate design with low leakage is proposed. Traditionally, the subthreshold leakage through a logic gate depends on the applied input vector. In order to reduce leakage power, we stack an extra transistor in the large leakage path. The proposed structure induces low leakage current under all possible inputs. Compared to the conventional CMOS logic circuit design, the simulation results show that the proposed logic circuits not only reduce significant leakage power dissipation, but also keep similar circuit performance as conventional CMOS logic circuits.
|出版狀態||Published - 2004 十二月 1|
|事件||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan|
持續時間: 2004 十二月 6 → 2004 十二月 9
|Other||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology|
|期間||04-12-06 → 04-12-09|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering