Leakage current reduction in CMOS logic circuits

Heng Yao Lin, Chi Sheng Lin, Lih Yih Chiou, Bin Da Liu

研究成果: Paper

5 引文 斯高帕斯(Scopus)

摘要

In this paper, a novel logic gate design with low leakage is proposed. Traditionally, the subthreshold leakage through a logic gate depends on the applied input vector. In order to reduce leakage power, we stack an extra transistor in the large leakage path. The proposed structure induces low leakage current under all possible inputs. Compared to the conventional CMOS logic circuit design, the simulation results show that the proposed logic circuits not only reduce significant leakage power dissipation, but also keep similar circuit performance as conventional CMOS logic circuits.

原文English
頁面349-352
頁數4
出版狀態Published - 2004 十二月 1
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
持續時間: 2004 十二月 62004 十二月 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家Taiwan
城市Tainan
期間04-12-0604-12-09

    指紋

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此

Lin, H. Y., Lin, C. S., Chiou, L. Y., & Liu, B. D. (2004). Leakage current reduction in CMOS logic circuits. 349-352. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.