Leveraging nMOS Negative Differential Resistance for Low Power, High Reliability Magnetic Memory

Shaodi Wang, Andrew Pan, Cecile Grezes, Pedram Khalili Amiri, Kang L. Wang, Chi On Chui, Puneet Gupta

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

We propose, demonstrate, and assess a nontunneling-based nMOS voltage-controlled negative differential resistance (V-NDR) concept for overcoming the intrinsic efficiency and reliability shortcomings of magnetic random access memory memories (MRAM). Using nMOS V-NDR circuits in series with MRAM tunnel junctions, we experimentally observe 40 times reduction in current during switching, enabling write termination and read margin amplification. Large scale Monte Carlo simulations also show 5X improvement in write energy savings and demonstrate the robustness of the scheme against device variability.

原文English
文章編號8024018
頁(從 - 到)4084-4090
頁數7
期刊IEEE Transactions on Electron Devices
64
發行號10
DOIs
出版狀態Published - 2017 十月

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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