TY - JOUR
T1 - Linearity improvement of cascode CMOS LNA using a diode connected NMOS transistor with a parallel RC circuit
AU - Chang, C. P.
AU - Chien, W. C.
AU - Su, C. C.
AU - Wang, Y. H.
AU - Chen, J. H.
PY - 2010
Y1 - 2010
N2 - A fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) using post-linearization technique, implemented in a 0.18 μm RF CMOS technology, is demonstrated. The proposed technique adopts an additional folded diode with a parallel RC circuit as an intermodulation distortion (IMD) sinker. The proposed LNA not only achieves high linearity, but also minimizes the degradation of gain, noise figure (NF) and power consumption. The LNA achieves an input third-order intercept point (IIP3) of +8.33 dBm, a power gain of 10.02 dB, and a NF of 3.05 dB at 5.5 GHz biased at 6mA from a 1.8 V power supply.
AB - A fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) using post-linearization technique, implemented in a 0.18 μm RF CMOS technology, is demonstrated. The proposed technique adopts an additional folded diode with a parallel RC circuit as an intermodulation distortion (IMD) sinker. The proposed LNA not only achieves high linearity, but also minimizes the degradation of gain, noise figure (NF) and power consumption. The LNA achieves an input third-order intercept point (IIP3) of +8.33 dBm, a power gain of 10.02 dB, and a NF of 3.05 dB at 5.5 GHz biased at 6mA from a 1.8 V power supply.
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U2 - 10.2528/PIERC10082411
DO - 10.2528/PIERC10082411
M3 - Article
AN - SCOPUS:79951987924
SN - 1937-8718
VL - 17
SP - 29
EP - 38
JO - Progress In Electromagnetics Research C
JF - Progress In Electromagnetics Research C
ER -