Linking Room- and Low-Temperature Electrical Performance of MOS Gate Stacks for Cryogenic Applications

K. H. Kao, C. Godfrin, A. Elsayed, R. Li, E. Simoen, A. Grill, S. Kubicek, I. P. Radu, B. Govoreanu

研究成果: Article同行評審

摘要

Based on MOSFETs with four different gate stacks, we extract the oxide trap density and transconductance from the low frequency noise and DC transfer characteristics at room temperature, respectively. With the same gate stacks, Hall mobility as a function of carrier density is and the critical density is extracted at low temperatures. These physical quantities are analyzed and correlated explicitly, offering a method to qualitatively compare the quality of the four gate stacks for cryogenic MOS devices, and providing further insight into the material physics at cryogenic temperatures.

原文English
頁(從 - 到)674-677
頁數4
期刊IEEE Electron Device Letters
43
發行號5
DOIs
出版狀態Published - 2022 5月 1

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 電氣與電子工程

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