Logic design using the PLAs with limited I/O pins and product terms

Yau Hwang Kuo, Ruey Rong Wang, Ling Yeung Kung

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

When commercial programmable logic arrays (PLA) are used in logic design, the limitation on the number of I/O pins and product terms is an important issue. For overcoming this problem, a logic decomposition method, which can decompose a complex Boolean function into several subfunctions adaptable to be realized in some commercially available PLAs, is proposed in this paper. Then a two-level AND-OR gate network is used to connect the PLAs for realizing the original Boolean function. In fact, this AND-OR gate network can also be implemented with a PLA chip. Therefore, this method, which realizes a large Boolean function with a multiple-level PLA network, provides a practical solution to the problem of logic design with PLA chips. This paper also describes a quick algorithm for minimizing the Boolean function to be realized by PLAs.

原文English
頁(從 - 到)27-31
頁數5
期刊Microprocessing and Microprogramming
23
發行號1-5
DOIs
出版狀態Published - 1988 三月

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

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