When commercial programmable logic arrays (PLA) are used in logic design, the limitation on the number of I/O pins and product terms is an important issue. For overcoming this problem, a logic decomposition method, which can decompose a complex Boolean function into several subfunctions adaptable to be realized in some commercially available PLAs, is proposed in this paper. Then a two-level AND-OR gate network is used to connect the PLAs for realizing the original Boolean function. In fact, this AND-OR gate network can also be implemented with a PLA chip. Therefore, this method, which realizes a large Boolean function with a multiple-level PLA network, provides a practical solution to the problem of logic design with PLA chips. This paper also describes a quick algorithm for minimizing the Boolean function to be realized by PLAs.
All Science Journal Classification (ASJC) codes
- 工程 (全部)