Logic testing of switch-level faults for CMOS unate networks

Yeong Ruey Shieh; Cheng W. Wu

Logic testing of switch-level faults for CMOS unate networks

Yeong Ruey Shieh, Cheng W. Wu

電機工程學系

研究成果: Paper › 同行評審

摘要

The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.

原文	English
頁面	212-215
頁數	4
出版狀態	Published - 1997 12月 1
事件	7th International Symposium on IC Technology, Systems and Applications ISIC 97 - Singapore, Singapore 持續時間: 1997 9月 10 → 1997 9月 12

Other

Other	7th International Symposium on IC Technology, Systems and Applications ISIC 97
國家/地區	Singapore
城市	Singapore
期間	97-09-10 → 97-09-12

All Science Journal Classification (ASJC) codes

電氣與電子工程
電子、光磁材料

其它文件與鏈接

引用此

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title = "Logic testing of switch-level faults for CMOS unate networks",

abstract = "The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.",

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N2 - The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.

AB - The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.

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M3 - Paper

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T2 - 7th International Symposium on IC Technology, Systems and Applications ISIC 97

Y2 - 10 September 1997 through 12 September 1997

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Logic testing of switch-level faults for CMOS unate networks

摘要

Other

All Science Journal Classification (ASJC) codes

其它文件與鏈接

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