Logic testing of switch-level faults for CMOS unate networks

Yeong Ruey Shieh, Cheng W. Wu

研究成果: Paper

摘要

The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.

原文English
頁面212-215
頁數4
出版狀態Published - 1997 十二月 1
事件7th International Symposium on IC Technology, Systems and Applications ISIC 97 - Singapore, Singapore
持續時間: 1997 九月 101997 九月 12

Other

Other7th International Symposium on IC Technology, Systems and Applications ISIC 97
國家Singapore
城市Singapore
期間97-09-1097-09-12

指紋

Switches
Monitoring
Testing
Design for testability
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

引用此文

Shieh, Y. R., & Wu, C. W. (1997). Logic testing of switch-level faults for CMOS unate networks. 212-215. 論文發表於 7th International Symposium on IC Technology, Systems and Applications ISIC 97, Singapore, Singapore.
Shieh, Yeong Ruey ; Wu, Cheng W. / Logic testing of switch-level faults for CMOS unate networks. 論文發表於 7th International Symposium on IC Technology, Systems and Applications ISIC 97, Singapore, Singapore.4 p.
@conference{bceff085c3074d9c9bc855fe6485e127,
title = "Logic testing of switch-level faults for CMOS unate networks",
abstract = "The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.",
author = "Shieh, {Yeong Ruey} and Wu, {Cheng W.}",
year = "1997",
month = "12",
day = "1",
language = "English",
pages = "212--215",
note = "7th International Symposium on IC Technology, Systems and Applications ISIC 97 ; Conference date: 10-09-1997 Through 12-09-1997",

}

Shieh, YR & Wu, CW 1997, 'Logic testing of switch-level faults for CMOS unate networks', 論文發表於 7th International Symposium on IC Technology, Systems and Applications ISIC 97, Singapore, Singapore, 97-09-10 - 97-09-12 頁 212-215.

Logic testing of switch-level faults for CMOS unate networks. / Shieh, Yeong Ruey; Wu, Cheng W.

1997. 212-215 論文發表於 7th International Symposium on IC Technology, Systems and Applications ISIC 97, Singapore, Singapore.

研究成果: Paper

TY - CONF

T1 - Logic testing of switch-level faults for CMOS unate networks

AU - Shieh, Yeong Ruey

AU - Wu, Cheng W.

PY - 1997/12/1

Y1 - 1997/12/1

N2 - The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.

AB - The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.

UR - http://www.scopus.com/inward/record.url?scp=1842780106&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=1842780106&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:1842780106

SP - 212

EP - 215

ER -

Shieh YR, Wu CW. Logic testing of switch-level faults for CMOS unate networks. 1997. 論文發表於 7th International Symposium on IC Technology, Systems and Applications ISIC 97, Singapore, Singapore.