摘要
The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.
| 原文 | English |
|---|---|
| 頁面 | 212-215 |
| 頁數 | 4 |
| 出版狀態 | Published - 1997 十二月 1 |
| 事件 | 7th International Symposium on IC Technology, Systems and Applications ISIC 97 - Singapore, Singapore 持續時間: 1997 九月 10 → 1997 九月 12 |
Other
| Other | 7th International Symposium on IC Technology, Systems and Applications ISIC 97 |
|---|---|
| 國家 | Singapore |
| 城市 | Singapore |
| 期間 | 97-09-10 → 97-09-12 |
指紋
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
引用此文
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Logic testing of switch-level faults for CMOS unate networks. / Shieh, Yeong Ruey; Wu, Cheng W.
1997. 212-215 論文發表於 7th International Symposium on IC Technology, Systems and Applications ISIC 97, Singapore, Singapore.研究成果: Paper
TY - CONF
T1 - Logic testing of switch-level faults for CMOS unate networks
AU - Shieh, Yeong Ruey
AU - Wu, Cheng W.
PY - 1997/12/1
Y1 - 1997/12/1
N2 - The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.
AB - The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.
UR - http://www.scopus.com/inward/record.url?scp=1842780106&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=1842780106&partnerID=8YFLogxK
M3 - Paper
AN - SCOPUS:1842780106
SP - 212
EP - 215
ER -