Logic testing of switch-level faults for CMOS unate networks

Y.-R. Shieh, Cheng-Wen Wu

研究成果: Conference contribution

原文English
主出版物標題7th International Symposium on IC Technology, Systems & Applications (ISIC)
出版地Singapore
頁面212-215
出版狀態Published - 1997 九月

引用此

Shieh, Y-R., & Wu, C-W. (1997). Logic testing of switch-level faults for CMOS unate networks. 於 7th International Symposium on IC Technology, Systems & Applications (ISIC) (頁 212-215).