摘要
The authors present a simple and fast online lossless compression design to encode the vector quantised indexes for 2-D still images. The computation complexity of the method is quite low and its memory requirement is small. Experimental simulations show that the proposed scheme achieves better compression efficiency than existing lossless index coding schemes. An efficient VLSI architecture for this scheme is developed and yields a processing rate of about 83.3 mega-indexes per second. The hardware architecture is implemented using an Altera FPGA chip. A demonstration system is also built by integrating the chip with an 8051 microprocessor to verify the performance of the VLSI architecture.
原文 | English |
---|---|
頁(從 - 到) | 109-117 |
頁數 | 9 |
期刊 | IEE Proceedings: Circuits, Devices and Systems |
卷 | 152 |
發行號 | 2 |
DOIs | |
出版狀態 | Published - 2005 4月 1 |
All Science Journal Classification (ASJC) codes
- 電氣與電子工程