Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding

Giun Lee Gwo, Chia Cheng Lo, Yuan Ching Chen, Sheau Fang Lei, He Yuan Lin, Ming Jiun Wang

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

This paper introduces a low complexity VLSI hardware architecture for entropy coding with increased throughput, based on the study of the statistical properties of the Context-based Adaptive Variable Length Coding (CAVLC) in AVC/H.264. These enhanced designs are due to the results of the statistical analyses, in which better symbol length prediction was achieved by breaking the recursive dependency among codewords for multi-symbol decoder implementation. The proposed CAVLC decoder can also easily meet real-time requirements for High Definition (HD) (1920x1080) applications, while the clock speed is operated only at 13 MHz under the best case scenario.

原文English
主出版物標題2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
頁面1229-1232
頁數4
DOIs
出版狀態Published - 2009
事件2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan
持續時間: 2009 五月 242009 五月 27

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Other

Other2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
國家Taiwan
城市Taipei
期間09-05-2409-05-27

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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