Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding

Giun Lee Gwo; Chia Cheng Lo; Yuan Ching Chen; Sheau Fang Lei; He Yuan Lin; Ming Jiun Wang

doi:10.1109/ISCAS.2009.5117984

Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding

Giun Lee Gwo, Chia Cheng Lo, Yuan Ching Chen, Sheau Fang Lei, He Yuan Lin, Ming Jiun Wang

電機工程學系

研究成果: Conference contribution

2 引文斯高帕斯（Scopus）

摘要

This paper introduces a low complexity VLSI hardware architecture for entropy coding with increased throughput, based on the study of the statistical properties of the Context-based Adaptive Variable Length Coding (CAVLC) in AVC/H.264. These enhanced designs are due to the results of the statistical analyses, in which better symbol length prediction was achieved by breaking the recursive dependency among codewords for multi-symbol decoder implementation. The proposed CAVLC decoder can also easily meet real-time requirements for High Definition (HD) (1920x1080) applications, while the clock speed is operated only at 13 MHz under the best case scenario.

原文	English
主出版物標題	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
頁面	1229-1232
頁數	4
DOIs	https://doi.org/10.1109/ISCAS.2009.5117984
出版狀態	Published - 2009
事件	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan 持續時間: 2009 5月 24 → 2009 5月 27

出版系列

名字	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN（列印）	0271-4310

Other

Other	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
國家/地區	Taiwan
城市	Taipei
期間	09-05-24 → 09-05-27

All Science Journal Classification (ASJC) codes

電氣與電子工程

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10.1109/ISCAS.2009.5117984

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引用此

Gwo, G. L., Lo, C. C., Chen, Y. C., Lei, S. F., Lin, H. Y., & Wang, M. J. (2009). Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding. 於 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 (頁 1229-1232). 文章 5117984 (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2009.5117984

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title = "Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding",

abstract = "This paper introduces a low complexity VLSI hardware architecture for entropy coding with increased throughput, based on the study of the statistical properties of the Context-based Adaptive Variable Length Coding (CAVLC) in AVC/H.264. These enhanced designs are due to the results of the statistical analyses, in which better symbol length prediction was achieved by breaking the recursive dependency among codewords for multi-symbol decoder implementation. The proposed CAVLC decoder can also easily meet real-time requirements for High Definition (HD) (1920x1080) applications, while the clock speed is operated only at 13 MHz under the best case scenario.",

author = "Gwo, {Giun Lee} and Lo, {Chia Cheng} and Chen, {Yuan Ching} and Lei, {Sheau Fang} and Lin, {He Yuan} and Wang, {Ming Jiun}",

year = "2009",

doi = "10.1109/ISCAS.2009.5117984",

language = "English",

isbn = "9781424438280",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "1229--1232",

booktitle = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009",

note = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 ; Conference date: 24-05-2009 Through 27-05-2009",

}

Gwo, GL, Lo, CC, Chen, YC, Lei, SF, Lin, HY & Wang, MJ 2009, Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding. 於 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009., 5117984, Proceedings - IEEE International Symposium on Circuits and Systems, 頁 1229-1232, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, 09-05-24. https://doi.org/10.1109/ISCAS.2009.5117984

TY - GEN

T1 - Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding

AU - Gwo, Giun Lee

AU - Lo, Chia Cheng

AU - Chen, Yuan Ching

AU - Lei, Sheau Fang

AU - Lin, He Yuan

AU - Wang, Ming Jiun

PY - 2009

Y1 - 2009

N2 - This paper introduces a low complexity VLSI hardware architecture for entropy coding with increased throughput, based on the study of the statistical properties of the Context-based Adaptive Variable Length Coding (CAVLC) in AVC/H.264. These enhanced designs are due to the results of the statistical analyses, in which better symbol length prediction was achieved by breaking the recursive dependency among codewords for multi-symbol decoder implementation. The proposed CAVLC decoder can also easily meet real-time requirements for High Definition (HD) (1920x1080) applications, while the clock speed is operated only at 13 MHz under the best case scenario.

AB - This paper introduces a low complexity VLSI hardware architecture for entropy coding with increased throughput, based on the study of the statistical properties of the Context-based Adaptive Variable Length Coding (CAVLC) in AVC/H.264. These enhanced designs are due to the results of the statistical analyses, in which better symbol length prediction was achieved by breaking the recursive dependency among codewords for multi-symbol decoder implementation. The proposed CAVLC decoder can also easily meet real-time requirements for High Definition (HD) (1920x1080) applications, while the clock speed is operated only at 13 MHz under the best case scenario.

UR - http://www.scopus.com/inward/record.url?scp=70350164288&partnerID=8YFLogxK

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DO - 10.1109/ISCAS.2009.5117984

M3 - Conference contribution

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SN - 9781424438280

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1229

EP - 1232

BT - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009

T2 - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009

Y2 - 24 May 2009 through 27 May 2009

ER -

Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding

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