摘要
In this paper, we propose a reduced complexity architecture for the active interference cancellation (AIC) technique. Computation power is saved mainly by exploiting the regularity of the matrix structure. The proposed architecture is implemented using fixed-point computation with low hardware cost. Simulation results show that the performance of the proposed scheme is almost the same as that of the original floating-point AIC scheme.
原文 | English |
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主出版物標題 | 2009 International Conference on Communications, Circuits and Systems, ICCCAS 2009 |
頁面 | 272-276 |
頁數 | 5 |
出版狀態 | Published - 2009 |
事件 | 2009 International Conference on Communications, Circuits and Systems, ICCCAS 2009 - Milpitas, CA, United States 持續時間: 2009 7月 23 → 2009 7月 25 |
Other
Other | 2009 International Conference on Communications, Circuits and Systems, ICCCAS 2009 |
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國家/地區 | United States |
城市 | Milpitas, CA |
期間 | 09-07-23 → 09-07-25 |
All Science Journal Classification (ASJC) codes
- 電腦網路與通信
- 硬體和架構
- 電氣與電子工程