Low-cost error tolerance scheme for 3-D CMOS imagers

Hsiu Ming Chang Chang, Jiun Lang Huang, Ding Ming Kwai, Kwang Ting Cheng, Cheng Wen Wu

研究成果: Article同行評審

6 引文 斯高帕斯(Scopus)

摘要

This paper presents an error tolerance scheme for 3-D CMOS imagers that are constructed by stacking a pixel array of imager sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) array using microbumps (μbumps) and through silicon vias (TSVs). To deliver high-quality images in the presence of single or multiple μbump, ADC, or TSV failures, we propose to interleave the connections from pixels to ADCs and recover the corrupted data in the ISPs. Key design parameters, such as the interleaving stride and the grouping ratio are determined by analyzing the employed error correction algorithm. Architectural simulation results demonstrate that the error tolerance scheme enhances the effective yield of an exemplar 3-D imager from 44% to 97%.

原文English
文章編號6186837
頁(從 - 到)465-474
頁數10
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
21
發行號3
DOIs
出版狀態Published - 2013 一月 1

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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