Low-cost post-bond testing of 3-D ICs containing a passive silicon interposer base

Chun Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng Wen Wu

研究成果: Article同行評審

6 引文 斯高帕斯(Scopus)

摘要

Through-silicon vias (TSVs) provide high-density vertical interconnects between dies and enable the creation of 3-D ICs having higher performance and lower power consumption than traditional 2-D ICs. A practical TSV-based 3-D integration approach is to place multiple dies (or die stacks) side by side on a passive silicon interposer base, in which there are TSVs and metal wires serving as interconnects. In this paper, we propose a post-bond design-for-test architecture and a test strategy for such interposer-based 3-D ICs. Functional package pins and interconnects are reused to build multibit parallel test access mechanisms (PTAMs), which provide post-bond test access with no or low extra area costs. Four PTAM architectures are presented, and the corresponding PTAM optimization algorithms are proposed which can quickly identify the best PTAM configuration to achieve the shortest test time. We also propose an algorithm for adding dedicated test interconnects to improve test bandwidth at the expense of extra microbumps and metal wires. Experimental results show that the proposed techniques are effective in test length (and therefore test time) reduction. Moreover, cost-benefit analysis results suggest that our approaches have lower total test costs compared with a base-case one-bit JTAG-only solution.

原文English
文章編號6680768
頁(從 - 到)2388-2401
頁數14
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
22
發行號11
DOIs
出版狀態Published - 2014 十一月 1

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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