Low-cost realization of multiple-input exclusive-OR gates

Kun Jin Lin, Cheng Wen Wu

研究成果: Conference article

5 引文 斯高帕斯(Scopus)

摘要

Several efficient CMOS two-input exclusive-OR (XOR) logic structures have been reported in the past. Based on these XOR gates, we propose two multiple-input XOR circuit configurations, which are smaller, faster, and run at a lower power level than conventional structures formed by directly connecting two-input XOR gates. For exclusive-OR sum-of-products circuits, four transistors can be saved for each product term.

原文English
頁(從 - 到)307-310
頁數4
期刊Proceedings of the Annual IEEE International ASIC Conference and Exhibit
出版狀態Published - 1995 十二月 1
事件Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA
持續時間: 1995 九月 181995 九月 22

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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