Several efficient CMOS two-input exclusive-OR (XOR) logic structures have been reported in the past. Based on these XOR gates, we propose two multiple-input XOR circuit configurations, which are smaller, faster, and run at a lower power level than conventional structures formed by directly connecting two-input XOR gates. For exclusive-OR sum-of-products circuits, four transistors can be saved for each product term.
|頁（從 - 到）||307-310|
|期刊||Proceedings of the Annual IEEE International ASIC Conference and Exhibit|
|出版狀態||Published - 1995 十二月 1|
|事件||Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA|
持續時間: 1995 九月 18 → 1995 九月 22
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering