Low-cost VLSI architecture design for non-separable 2-D Discrete Wavelet Transform

Ming Hwa Sheu, Ming-Der Shieh, Sheng Wei Liu

研究成果: Paper

4 引文 斯高帕斯(Scopus)

摘要

This paper presents an architecture for 2-D image decomposition of discrete wavelet transform. In order to avoid the memory transpose problem, we use non-separable approach instead of separable one. Besides, based on the input data reuse concept, a parallel-pipelined architecture is proposed. The main characteristics of this architecture include : (1) needless memory transposition; (2) lower hardware cost; (3) shorter latency; (4) suitable VLSI implementation. Finally, all components in our architecture are simulated based on the accuracy requirement and realized as a single chip physically.

原文English
頁面1217-1220
頁數4
出版狀態Published - 1997 十二月 1
事件Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Sacramento, CA, USA
持續時間: 1997 八月 31997 八月 6

Other

OtherProceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2)
城市Sacramento, CA, USA
期間97-08-0397-08-06

    指紋

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此

Sheu, M. H., Shieh, M-D., & Liu, S. W. (1997). Low-cost VLSI architecture design for non-separable 2-D Discrete Wavelet Transform. 1217-1220. 論文發表於 Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2), Sacramento, CA, USA, .